1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method.
Priority is claimed on Japanese Patent Application No. 2011-066059, filed Mar. 24, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
An image pickup device, such as a still camera, a video camera, a medical endoscope camera, or an industrial endoscope camera, processes image data containing data of a great number of pixels (hereinafter referred to as “pixel data”) with the increase of the number of pixels and speed of the image pickup device. In such an image pickup device, a memory for temporarily storing image data obtained by photographing is used when each processing block in the image pickup device processes the image data. Image data in each processing step is temporarily stored in the memory.
FIG. 16 is a block diagram illustrating a schematic configuration of an image pickup device in accordance with the related art. For example, image data processing in a photographing operation of the image pickup device shown in FIG. 16 is performed in the following order.
(Step 1)
First, an image pickup processing unit, for example, transmits image data obtained by a CCD (Charge Coupled Device) solid-state image pickup device to a memory via an output DMA (Direct Memory Access) unit to temporarily store the image data.
(Step 2)
Subsequently, an image processing unit reads the image data temporarily stored in the memory via an input DMA unit. The image processing unit performs image processing for recording or display on the read image data. The image processing unit then transmits the processed image data to the memory via the output DMA unit to temporarily store the image data.
(Step 3)
Subsequently, a display processing unit reads the image data subjected to image processing for display via an input DMA unit and causes a display device to display the image data.
Thus, in the image pickup device, the preceding processing block temporarily stores the image data in the memory. The subsequent processing block reads the image data stored in the memory and performs a next process. Thus, as respective processing blocks in the image pickup device perform delivery of the image data, which is a processing target, through the memory, processes of the image pickup device are sequentially performed.
In recent years, it has been desirable for an image pickup device such as a still camera, a video camera or the like to be able to be continuously used for a long time. Accordingly, there is a need for a technique for reducing power consumption of an electrical circuit of the image pickup device. One method of reducing the power consumption of the image pickup device includes a method of increasing a transfer rate for image data between each processing block (electrical circuit) and a memory. The increase of the transfer rate for image data, for example, may be realized by increasing a frequency of an operation clock of the image pickup device or shortening a transfer period of time of the image data between the processing block and the memory. This method reduces power consumption due to transfer of the image data by increasing the transfer rate of the image data.
As a technique of shortening a transfer period of time of image data between the processing block and the memory, a packing technique as disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 (hereinafter referred to as Patent Document 1) is known. The packing technique disclosed in Patent Document 1 is a technique of extending a bus width of a data bus used when each pixel data in the image data is transferred to a memory and arranging (packing) a plurality of adjacent pixel data in the data bus to transfer a plurality of pixel data at a single time. Using this technique, the number of data transfers required to transfer all pixel data can be further reduced as compared with conventional data transfer in which pixel data is transferred pixel by pixel, and the period of time for data transfer of the image data can be shortened. FIG. 17 is a diagram illustrating an example of an arrangement of image data. For example, when pixel data as shown in FIG. 17 obtained from a 16×16 Bayer arrangement CCD is transferred to a memory, in the packing technique disclosed in Patent Document 1, pixel data for 4 pixels is one transfer unit, thus reducing a transfer period of the image data to ¼. Accordingly, it is possible to reduce power consumption of an electrical circuit in the image pickup device, unlike a case in which pixel data is transferred to the memory pixel by pixel.
As a technique of further shortening the transfer period of image data, a packing method using burst transfer of DMA is considered. This is a method in which one burst, which is a memory access unit at a prescribed certain number of cycles, is considered a pixel data packing unit. FIGS. 18A and 18B are diagrams illustrating an example of pixel data packing in accordance with the related art. FIG. 18A illustrates a packing method disclosed in Patent Document 1. An example in which the pixel data shown in FIG. 17 is packed is shown in FIG. 18A. FIG. 18B illustrates an example in which the pixel data shown in FIG. 17 is packed in a burst unit. An example in which a bus width (hereinafter referred to as “memory bus width”) of a data bus used when the pixel data is transferred to the memory (hereinafter referred to as “memory bus”) is 32 bits, and memory access for one cycle in burst transfer (hereinafter referred to as “one transfer”) is performed four times, that is, one burst transfer is performed through four transfers, is shown in FIGS. 18A and 18B. An example in which resolution of pixel data of one pixel, that is, a bit number of the pixel data is 9, 10, 12, and 14 from top to bottom, is shown in FIGS. 18A and 18B.
In the packing method disclosed in Patent Document 1 shown in FIG. 18A, pixel data for two pixels per one transfer can be arranged on a memory bus, and pixel data for 8 pixels per one burst can be transferred to the memory. On the other hand, in the burst unit-based packing method shown in FIG. 18B, pixel data for 14, 12, 10, and 9 pixels can be transferred to the memory. In the packing method disclosed in Patent Document 1, since pixel data is arranged (packed) in the memory bus width, that is, in a unit of one transfer, a sum of bit numbers of a plurality of arranged pixel data must not exceed the memory bus width. Accordingly, in the packing method disclosed in Patent Document 1, there are bits to which pixel data cannot be allocated (hereinafter referred to as “unused bits”) within the memory bus width. On the other hand, in the burst unit-based packing method, since pixel data is arranged (packed) in units of bursts, even when a sum of bit numbers of a plurality of arranged pixel data exceeds the memory bus width, the pixel data can be arranged (packed) in a next transfer as long as the sum does not exceed one burst, as in FIG. 18B. That is, in the burst unit-based packing method, even when the memory bus width is not an integer times the resolution of pixel data, the pixel data can be arranged (mapped) over one transfer unit, which can reduce the number of unused bits. Accordingly, in the burst unit-based packing method, much pixel data can be transferred to the memory in the same time, that is, the transfer period of time of the image data can be shortened, and the power consumption of the electrical circuit in the image pickup device can be further reduced, as compared with the packing method disclosed in Patent Document 1.
In general, when data change (change (inversion) of data “0”→“1” or “1”→“0”) is less, power consumption is known to be lower. Accordingly, reducing the power consumption of the image pickup device by reducing the data change on the memory bus between each processing block (electrical circuit) and a memory in an image pickup device is also considered. FIGS. 19A, 19B, 19C and 19D are diagrams illustrating a relationship between the data change on the data bus (memory bus) between the processing block and the memory in the image pickup device and the power consumption. FIG. 19A illustrates an example in which a bus width of a memory bus between the image pickup processing unit and the memory in the image pickup device shown in FIG. 16 is 32 bits. The data change on the memory bus is schematically shown in FIGS. 19B to 19D. In the example of FIGS. 19A, 19B, 19C and 19D, power consumption is lowest in the case of FIG. 19B in which there is no data change on the memory bus, and highest in the case of FIG. 19D in which there are the most data changes on the memory bus.
It can be seen from the above that if there is a great amount of change in pixel data between two continuous transfers (e.g., pixel data in first and second transfers of each burst transfer shown in FIGS. 18A and 18B) in the burst transfer between each processing block and the memory in the image pickup device, power consumption due to the transfer of the image data increases. That is, the power consumption due to the transfer of the image data varies in proportion to the number of the same bits (bit number) on the memory bus changing between the two transfers.
In general, there is expected to be a small amount of change in data between adjacent pixels in image data, and bits whose values are being inverted are expected to be less than bits whose values are not being inverted when the same bits of each pixel data of adjacent pixels are compared. FIGS. 20A and 20B are diagrams illustrating an example of a data arrangement state in a pixel data packing method in accordance with the related art. Here, when the packing method disclosed in Patent Document 1 and the burst unit-based packing method, which are shown in FIGS. 18A and 18B, are compared with each other, the power consumption due to the transfer of the image data is lower in the packing method disclosed in Patent Document 1 in which the same bits are aligned in pixel data with the same colors, as shown in FIGS. 20A and 20B. Further, FIGS. 20A and 20B show a case in which the bit number of pixel data of one pixel is 9 in the packing method disclosed in Patent Document 1 and the burst unit-based packing method shown in FIGS. 18A and 18B.
More specifically, in the packing method disclosed in Patent Document 1 shown in FIG. 20A, least significant bits of the memory bus shown in a range A are all the same bits (least significant bits) of pixel data with the same colors. On the other hand, in the burst unit-based packing method shown in FIG. 20B, least significant bits of the memory bus shown in a range B are all different bits of pixel data having different colors. It can be seen from this that, when locations of bits of pixel data arranged on the memory bus are made different between two continuous transfers by packing the image data in a burst unit, a change amount of the same bits on the memory bus becomes great and the power consumption due to the transfer of the image data increases.
That is, in the packing method disclosed in Patent Document 1 shown in FIG. 20A, the power consumption due to the transfer of the image data is low, but data transfer efficiency is low. In the burst unit-based packing method shown in FIG. 20B, the data transfer efficiency is low, but the power consumption due to the transfer of the image data is high.
Thus, more pixel data is arranged on the memory bus when packing the pixel data into the burst units. As a result, the transfer period of time of the pixel data can be shortened and the power consumption due to transfer of the image data can be reduced. However, since locations of bits of the pixel data arranged on the memory bus are different between two continuous transfers, sufficient reduction of the power consumption due to the transfer of the image data cannot be obtained.
FIG. 21 is a diagram illustrating another example of a data arrangement state in the pixel data packing method in accordance with the related art. In the packing method disclosed in Patent Document 1, for example, pixel data for 3 pixels can be arranged (packed) in one transfer to pack the pixel data, as shown in FIG. 21. However, in this case, for example, least significant bits of a memory bus shown in a range C are the same bits (least significant bits) of the pixel data, but are pixel data having different colors. Pixel data having different colors is highly likely to be greatly different in value, and even in the packing method disclosed in Patent Document 1, the power consumption due to the transfer of the image data is not reduced due to the pixel data arrangement in one transfer.